1. Field of The Invention
This invention relates to a metal-insulation-silicon (hereunder abbreviated as MIS) type semiconductor device, which can be employed as, for example, a read-only memory, and a method for producing an MIS type semiconductor device.
2. Description of The Related Art
In recent years, there has been a marked tendency to develop a large capacity and highly-integrated semiconductor device. Moreover, there has been increased a demand for a very fine semiconductor device. Thus, a layout of a semiconductor pattern and a structure of a semiconductor device, which are more advantageous for producing a very fine semiconductor device (namely, for microminiaturizing a semiconductor device), are required. This holds true for a read-only memory.
Meanwhile, a threshold voltage of an MIS type transistor can be controlled according to the kinds and concentrations of impurities to be added to a semiconductor substrate, which is employed as a channel, in a diffusion process. In a read-only memory, information is selectively stored according to whether or not an operating threshold voltage of a gated transistor is greater than a reference voltage. An example of a conventional MIS type semiconductor device (hereunder sometimes referred to as a first conventional MIS type semiconductor device), as well as a method for producing such a conventional MIS type semiconductor device, will be described hereinbelow by referring to FIGS. 8 and 9.
FIG. 8 is a sectional view of the first conventional MIS type semiconductor device. As illustrated in this figure, the first conventional MIS type semiconductor device consists of a gate oxidation film 132 formed on a silicon substrate 131, a plurality of gate electrodes comprised of a gate-electrode polysilicon layer 133 and connected in series with one another, a source diffusion layer 134 and a drain diffusion layer 135 which are formed in the silicon substrate 131, n-type diffusion layers 136 formed between the gate electrodes, an n-type diffusion layer 139 for forming a depletion type metal-oxide semiconductor (hereunder abbreviated as DMOS) channel, an insulation layer (hereunder sometimes referred to as an inter-layer insulation film) 137 and an aluminum wire 138.
FIGS. 9(a) to 9(d) are sectional views of the first conventional MIS type semiconductor device for illustrating the method for producing the first conventional MIS type semiconductor device. Hereinafter, this method will be described by referring to these figures.
First, as shown in FIG. 9(a), a photoresist mask 140 for separating an n-type diffusion area is formed on the silicon substrate 131. Then, an n-type ion implantation is performed by shooting streams of ions 141 and using the photoresist mask 140 as a mask for the ion implantation. Thus n-type impurities are selectively diffused in the silicon substrate 131. As the result, the diffusion layer 139 for forming a DMOS channel is formed in order to control the threshold voltage of the conventional semiconductor device.
Next, as shown in FIG. 9(b), a photoresist mask 142 for forming a gate electrode is formed after the gate oxidation film 132 and the gate-electrode polysilicon layer 133 are formed.
Subsequently, as shown in FIG. 9(c); an etching of the gate-electrode polysilicon layer 133 is performed by using the photoresist mask 142 as a mask for the etching process. Then, n-type impurities are diffused by effecting an n-type ion implantation of streams of ions 143. Thus, the source diffusion layer 134, the drain diffusion layer 135 and the diffusion layers 136 are simultaneously formed.
Next, as shown in FIG. 9(d), the inter-layer insulation film 137 and the aluminum wire 138 are formed.
In the conventional MIS type semiconductor device produced as above described, the n-type diffusion layer 139 for forming a DMOS channel is present under the second gate electrode from left as viewed in FIG. 8. Thus the second transistor from left becomes a DMOS. In contrast, each of the other transistors (namely, the first, third and fourth transistors from left) is an enhancement type MOS (hereunder abbreviated as EMOS).
As is understood from the foregoing description, a read-only memory employing the first conventional MIS type semiconductor device has a structure in which data stored in a transistor thereof is discriminated as 1 or 0 according to which of DMOS and EMOS the transistor is.
A memory cell comprised of the first conventional MIS type semiconductor device constructed described above has a structure commonly called a single-layer polysilicon NAND type gate. In recent years, this structure is employed in many memory cells of mass read-only memories because of the fact that only one contact is provided therein correspondingly to a plurality of gate electrodes and thus this structure is favourable to realization of a highly integrated circuit.
Notwithstanding such an advantage, the first conventional MIS type semiconductor device and the method for producing such a conventional semiconductor device have the following drawbacks.
First, a period of time from the beginning of a programming of a read-only memory to the completion thereof is long, because the n-type diffusion layer 139 for forming a DMOS channel is formed before the gate electrodes are formed.
As a countermeasure to eliminate this drawback, it can be considered to form a diffusion layer made of impurities in a silicon substrate by performing an ion implantation posterior to the formation of the gate electrodes by accelerating ions to high velocity, which is sufficient to cause the ions to penetrate the gates. Such a countermeasure, however, has defects in that it requires an ion implantation apparatus which can accelerate ions to high energies in the range of several hundred kilo-electronvolts (KeV) to several mega-electronvolts (MeV) and in that the throughput of such an ion implantation apparatus becomes extremely low because a large quantity of ions to be accelerated is needed due to the facts that it is difficult to obtain a large beam current and that the gates hinder ions from reaching the silicon substrate.
Moreover, an ion implantation to be effected by accelerating ions to high velocity is attended with harmful effects that a device-isolation failure becomes liable to take place due to an occurrence of penetration of the n-type impurities through a device-isolation oxidation film. Thus a countermeasure to the penetration of the n-type impurities (for example, employment of trench isolation or a thick isolation oxidation film) becomes further needed.
Second, it is hard to realize a high-speed operation because the plurality of gate electrodes are arranged in series with one another and thus transistors of each memory cell cannot draw a large electric current (namely, cannot have large current driving ability).
The current flowing through the transistor of each memory cell depends on characteristics of the EMOS and DMOS transistors thereof.
Hereinafter, two respects noted by the inventor of the present invention to realize a high-speed operation of an MIS type semiconductor device will be described.
Generally, the transconductance g.sub.me of an MOS transistor is obtained by the following equation: EQU g.sub.me =g.sub.m /(1+R.sub.s .times.g.sub.m)
where R.sub.s denotes the resistance (hereunder sometimes referred to as the source resistance) of the source area of the MOS transistor; and g.sub.m the transconductance thereof in case where the source resistance R.sub.s is neglected.
Namely, when the source resistance R.sub.s increases, the transconductance g.sub.me is extremely degraded. As the result, characteristics such as an amplification factor and a switching speed of the MOS transistor are deteriorated.
In case of the device of the present invention, the characteristics of an MOS transistor can be improved by decreasing the source resistance R.sub.s of the MOS transistor.
Moreover, generally, in case where a diffusion layer made of n-type impurities is formed in a silicon substrate by an ion implantation or the like in order to form a channel of a DMOS transistor, the electrical resistance tends to decrease and the current driving ability of the DMOS transistor is apt to increase in proportion as the concentration of impurities is risen by increasing a quantity of implanted ions.
However, the elements of the impurities, of which the quantity exceeds a solid solubility limit, cannot dissolve in a silicon layer. Therefore, the quantity of the impurities, which can dissolve in a silicon layer, saturates at a certain value of the electrical resistance. It is, accordingly, difficult to make the value of the electrical resistance lower than the certain one thereof. Even if what is called an activation rate of ions of the impurities are increased, the electrical resistance can be lowered only to a specific value thereof. Instead, the diffusion layer of the impurities in the silicon layer is substantially extended as the result of an annealing or heat treatment for increasing the activation rate. This is disadvantageous to the production of a very fine memory element.
In case of the device of the present invention, the electrical resistance of an area corresponding to a channel of the DMOS transistor is lowered to have the same effects as would be obtained in case of improving the current driving ability of a DMOS transistor.
It is, therefore, an object of the present invention to provide an MIS type semiconductor device which can improve the transconductance of an enhancement type transistor thereof and characteristics of the transistors thereof to realize a high-speed operation thereof.
Further, it is another object of the present invention to provide a method, by which such an MIS type semiconductor device can stably be produced or fabricated.
Next, another example of a conventional MIS type semiconductor device (hereunder sometimes referred to as a second conventional MIS type semiconductor device), as well as a method for producing such a conventional MIS type semiconductor device, will be described hereinbelow by referring to FIGS. 11(a) and 11(b).
FIG. 11(a) is a plan view of a primary part of a layout of the second conventional MIS type semiconductor device.
FIG. 11(a) illustrates the layout of the semiconductor device comprised of a device-isolation region 201, memory-cell transistor gate electrode regions 202, selection line transistor gate electrode regions 203, an n-type diffusion region 217 for forming a DMOS channel, a drain region 218 and a contact pattern region 205 for forming a contact which touches the region 218.
Data is written to a read-only memory, which is produced by using this layout, according to which of DMOS and EMOS transistors a memory cell, to which the data is written, has correspondingly to the presence or absence of the n-type diffusion region 217.
In case of using the conventional patter layout, there is necessity of separating the layout pattern from gate electrode region by a distance of an overlapping margin 206 for forming the contact as a limit to the layout of the contact patter region 205.
This results in that the distance 207 between the selection line transistor gate electrode regions 203, which are respectively located at end portions of couples of the regions 203 upwardly and downwardly from the contact pattern region 205 as viewed in FIG. 11(a), should be more than a distance obtained by adding a length, which is twice the overlapping margin 206, to the length of the contact pattern region 205 in the vertical direction thereof as viewed in this figure.
FIG. 11(b) is a sectional view of the primary part of the layout of the second conventional MIS type semiconductor device, taken along the vertical line passing through the center of the contact pattern region 205 of FIG. 11(a). In FIG. 11(b), reference numeral 208 denotes a silicon substrate; and 219 a device-isolation oxidation film. Reference numerals 209 and 210 designate a memory-cell transistor gate electrode and a selection line transistor gate electrode 210, respectively, each of which has a gate oxidation film and a gate electrode polysilicon layer. Further, reference numeral 211 represents a drain diffusion layer formed in the silicon substrate 208; 215 an inter-layer insulation film; and 216 an aluminum wire employed as a bit line.
Incidentally, the n-type diffusion region for forming a DMOS channel and the n-type diffusion region provided between the gate electrodes are not shown in the sectional view of FIG. 11(b). However, these n-type diffusion regions are present in a portion, in which the device-isolation oxidation film 219 is not present, of the device.
Further, the overlapping margin 206 for forming the contact, as well as the distance 207 between the selection line transistor gate electrode regions 210, is shown in this sectional view.
A memory cell comprised of the second conventional MIS type semiconductor device constructed as shown in FIGS. 11(a) and 11(b) also has a structure commonly called a single-layer polysilicon NAND type gate. This conventional technique, however, has a drawback in that it is disadvantageous to fabrication of a very fine semiconductor device because an overlapping margin for forming an extra contact is required in case of fabricating a further highly integrated device.
Moreover, this conventional technique has another drawback in that the interconnection cannot stably be formed because an aspect ratio of a contact (namely, a ratio of the contact's depth to the contact's diameter) formed in a drain region and an aspect ratio of a contact formed in a source region are large.
Furthermore, this conventional technique has a further drawback in that a period of time from the beginning of a programming of a read-only memory to the completion thereof is long, because an n-type diffusion layer for forming a DMOS channel is formed before gate electrodes are formed.
Additionally, similarly as in case of the first conventional MIS type semiconductor device, the second conventional MIS type semiconductor device has still another drawback in that it is disadvantageous to a high-speed operation because a plurality of gate electrodes are arranged in series with one another in the pattern layout and thus transistors of each memory cell cannot draw a large electric current (namely, cannot have large current driving ability) which depends on characteristics of the EMOS and DMOS transistors thereof. The inventor of the present invention takes note of the two respects described above in order to realize a high-speed operation of an MIS type semiconductor device.
It is, therefore, a further object of the present invention to provide an MIS type semiconductor device which can be microminiaturized and can improve the transconductance of an enhancement type transistor thereof and can make the resistance of a region corresponding to a channel of a DMOS transistor low in order to have similar effects as obtained by improving the current driving ability of the DMOS transistor, thereby realizing a high-speed operation thereof, and which can shorten a period of time from the beginning of a programming of a read-only memory to the completion thereof.